The present invention relates to the design of a scan cell, and more specifically, to the design of a scan cell that changes the latency and power consumption in a scan chain based on a scan enable signal.
After an integrated circuit is manufactured, tests are performed on the integrated circuit to detect whether the integrated circuit has manufacturing defects. Testing techniques can detect if functional logic in the integrated circuit have been properly fabricated and function properly. In a typical system on chip, scan based testing such as Automatic Test Pattern Generation (ATPG) and Logic Built in Self Test (LBIST) are commonly used methodologies to detect manufacturing defects in an integrated circuit.